Single– φ Full Wave Controlled Rectifier (R Load)
The circuit include 4 thyristors T1, T2, T3 and T4, a voltage source Vs and a R Load. During the positive 1/2 of cycle of the input voltage, the thyristors T1 & T2 is forward biased however it does now no longer conduct till a gate signal is carried out to it.
When a gate pulse is given to the thyristors T1 & T2 at ωt = α, it receives turned ON and starts to conduct. When the T1 & T2 is ON, the enter voltage is applied to the load through the direction Vs- T1- Load-T2-Vs.
Here the load gets voltage throughout each the 1/2 of cycles. The common value of output voltage may be various through various the firing angle α. Single– φ Full Wave Controlled Rectifier (R Load) The waveform indicates the plot of input voltage, gate current, output voltage, output current and voltage throughout thyristor.
The plot of input voltage, gate current, output voltage, output current, and voltage across the thyristor is shown in the waveform.
Single– φ Full Wave Controlled Rectifier (RL Load) Mid – Point Converter
The circuit consist of thyristors T1 and T2, a centre tap transformer, a voltage source Vs and a RL Load. During the positive 1/2 of cycle of the input voltage, the thyristor T1 is forward biased however it does now no longer conduct till a gate signal is applied to it. When a gate pulse is given to the thyristor T1 at ωt = α, it receives grew to become ON and starts to behavior.
When the thyristor T1 is ON, the input voltage is applied to the load however because of the inductor present in the load, the current through the load builds up slowly through the direction A-T1-Load-N-A. During the negative 1/2 of cycle, T2 is forward biased, the thyristor T1 receives reverse biased however the current through the thyristor T1 isn’t always 0 because of the inductor and T1 does now no longer turns OFF. The current through the inductor starts to decay to 0 and T1 conducts for a small period in negative 1/2 of cycle.
So right here each the thyristor will conduct for some period in the negative 1/2 of cycle. The load gets voltage throughout each the 1/2 of cycles. The common value of output voltage may be various via way of means of various the firing angle α.
The circuit diagram is shown below.
Throughout the thyristor, the waveform depicts the plot of input voltage, gate current, output voltage, output current, and voltage.
Single– φ Full Wave Controlled Rectifier (RL Load) Bridge Converter
The circuit consist of 4 thyristors T1, T2, T3 and T4, a voltage source Vs and a RL Load. During the positive 1/2 of cycle of the input voltage, the thyristors T1 & T2 is ahead biased however it does now no longer behavior till a gate signal is applied to it. When a gate pulse is given to the thyristors T1 & T2 at ωt = α, it receives turned ON and starts to conduct.
When the T1 & T2 is ON, the input voltage is carried out to the load however because of the inductor present in the load, the current through the weight builds up slowly through the direction Vs-T1- Load-T2-Vs. During the negative 1/2 of cycle, T3 & T4 is forward biased, the thyristor T1 & T2 gets opposite biased however the modern-day thru them isn’t always 0 because of the inductor and does now no longer turns OFF. The current through the inductor starts to decay to 0 and T1 & T2 conducts for a small period in negative 1/2 of cycle..
When a gate pulse is given to the thyristor T3 & T4 at ωt = π+α, it receives turned ON and starts to conduct. When the thyristor T3 & T4 is ON, the load current shifts its direction to T3 & T4 and turns OFF T1 & T2 at ωt = π+α. When T3 & T4 is ON, the current through the load builds up slowly through the direction Vs.T3-Load-T4-Vs.
So right here all of the thyristor will conduct for some period in the negative 1/2 of cycle. The load gets voltage throughout each the 1/2 of cycles. The common value of output voltage may be various through various the firing angle α.
Single– φ Full Wave Controlled Rectifier (RL with FD)
The circuit consist of 4 thyristors T1, T2, T3 and T4, a voltage source Vs, a RL Load and a freewheeling diode throughout the weight. During the superb 1/2 of cycle of the input voltage, the thyristors T1 & T2 is forward biased however it does now no longer conduct till a gate signal is carried out to it.
When a gate pulse is given to the thyristors T1 & T2 at ωt = α, it receives turned ON and starts to conduct. When the T1 & T2 is ON, the input voltage is carried out to the load however because of the inductor present in the load, the current through the load builds up slowly through the direction Vs-T1- Load-T2-Vs.
During the negative 1/2 of cycle (at ωt = π), T3 & T4 is ahead biased, the thyristor T1 & T2 receives reverse biased. The current shifts its direction to the freewheeling diode and circulates thru the loop FD-R-L-FD. Thus T1 & T2 turns off at ωt = π . When a gate pulse is given to the thyristor T3 & T4 at ωt = π+α, it receives turned ON and starts to conduct.
When T3 & T4 is ON, the current thru the weight builds up slowly through the direction Vs-T3-Load-T4-Vs. During the next positive 1/2 of cycle (at ωt = 2π), T1 & T2 is forward biased, the thyristor T3 & T4 receives reverse biased.
The current shifts its direction to the freewheeling diode and circulates through the loop FD-R-L-FD. Thus T3 & T4 turns off at ωt = 2π . So right here all of the thyristor will conduct simplest in the positive 1/2 of cycle. The load receives voltage throughout each the 1/2 of cycles. The common value of output voltage may be various through various the firing angle α.
The waveform indicates the plot of input voltage, gate current, output voltage, output current and voltage throughout thyristor
